1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly relates to an operational amplifier that is not much influenced by an offset voltage.
2. Description of the Related Art
Conventionally, an operational amplifier was typically configured of bipolar transistors. However, recently, the operational amplifier has been also configured of MOS transistors in many cases due to the necessity of integration with a MOS (petal Oxide Semiconductor) circuit and the request of a low power. In order to form the operational amplifier by using the MOS transistors, the circuit configuration different from the operational amplifier configured of the bipolar transistors is adopted because of the analog characteristics peculiar to the MOS transistor. As one of application fields of the operational amplifier configured of the MOS transistors, there is a TFT_LCD (Thin Film Transistor Liquid Crystal Display) driver LSI (Large Scale Integrated Circuit). This LCD driver LSI contains therein a plurality of operational amplifiers of a voltage follower configuration for a γ compensation gradation voltage generating circuit. In particular, the device in which an offset voltage between the plurality of operational amplifiers is small is required. This is because even the voltage difference of 10 mV can be recognized as a different gradation by a human's eye from the characteristic of TFT_LCD. Thus, this field requires the MOS operational amplifier of a very small offset voltage.
FIGS. 1A and 1B are circuit diagrams showing a configuration example of an operational amplifier applied to a drive a conventional image display. This conventional operational amplifier is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-249623). This conventional operational amplifier includes two P-channel MOS transistors MP11 and MP12 of a differential pair, a constant current source I11, N-channel MOS transistors MN11 and MN12 of a current mirror circuit, an N-channel MOS transistor MN13, a constant current source 112, a phase compensation capacitor C11, break type switches S11, S14, S16 and S18, and make type switches S12, S13, S15 and S17.
A drain of one P-channel MOS transistor MP11 of the differential pair is connected to a drain of the N-channel MOS transistor MN11. Also, a drain of the other P-channel MOS transistor MP12 forming the differential pair is connected to a drain of the N-channel MOS transistor MN12. The constant current source I11 is inserted between a positive power source VDD and a source commonly connected to the P-channel MOS transistors MP11 and MP12 and biases this differential pair. The N-channel MOS transistors MN11 and MN12 of a current mirror structure function as an active load of the differential pair, and converts an input differential signal into a single end signal. The N-channel MOS transistor MN13 forms an amplifying circuit at a second stage. The constant current source I12 is inserted between the positive power source VDD and a drain of the N-channel MOS transistor MN13 and acts as an active load of this N-channel MOS transistor MN13. The phase compensation capacitor C11 is connected between a gate and drain of the N-channel MOS transistor MN13.
The break type switch S11 is connected between a gate and drain of the N-channel MOS transistor MN11. The make type switch S12 is connected between a gate and drain of the N-channel MOS transistor MN12. The make type switch S13 is connected between the drain of the N-channel MOS transistor MN11 and the gate of the N-channel MOS transistor MN13. The break type switch S14 is connected between the drain of the N-channel MOS transistor MN12 and the gate of the N-channel MOS transistor MN13. The make type switch S15 is connected between an output terminal Vout and the gate of the P-channel MOS transistor MP12. The break type switch S16 is connected between the output terminal Vout and the gate of the P-channel MOS transistor MP11. The make type switch S17 is connected between an input terminal Vin and the gate of the P-channel MOS transistor MP11. The break type switch S18 is connected between the input terminal Vin and the gate of the P-channel MOS transistor MP2.
Those switches S11 to S18 are all linked and controlled, and switched for every frame. FIG. 1A shows a state in case of the odd-numbered frame, and FIG. 1B shows a state in case of the even-numbered frame. In the operational amplifier shown in FIGS. 1A and 1B, when the switch S11 is closed, the drain of the N-channel MOS transistor MN12 serves as its single end output, and when the switch S12 is closed, the drain of the N-channel MOS transistor MN11 serves as the single end output. In this way, since a node of the single end output is switched based on the states of the switches S11 and S12, the output node is selected through the switch S13 and the switch S14. The signal which is selected through the switch S13 and the switch S14 is supplied to the gate of the N-channel MOS transistor MN13 serving as the output transistor. At this time, the constant current source I12 acts as the active load of the N-channel MOS transistor MN13. The drain of the N-channel MOS transistor MN13 serves as the output terminal Vout. The phase compensation capacitor C11 functions for the phase compensation as a mirror capacitance.
Since this operational amplifier is used as a buffer amplifier, a so-called voltage follower connection is established in which an inversion input terminal and an output terminal are commonly connected. When the switches S11 to S14 are switched, the inversion input terminal may become the gate of the P-channel MOS transistor MP11 or the gate of the P-channel MOS transistor MP12. This is switched through the switches S15; and S16. In response to the switching, a non-inversion input terminal is switched. Thus, this is switched through the switches S17 and S18. That is, when the switch S11 and the switch S14 are closed, the inversion input terminal serves as the gate of the P-channel MOS transistor MP11. Thus, at this time, the switch S16 is closed, and the gate of the P-channel MOS transistor MP11 serving as the inversion input terminal and the output terminal Vout are commonly connected, which serve as the voltage follower connection. Since the non-inversion input terminal serves as the gate of the P-channel MOS transistor MP12, the switch S18 is closed. Then, it is connected to the input terminal Vin. Inversely, when the switch S12 and the switch S13 are closed, the inversion input terminal serves as the gate of the P-channel MOS transistor MP12. Thus, at this time, the switch S15 is closed, and the gate of the P-channel MOS transistor MP12 serving as the inversion input terminal and the output terminal Vout are commonly connected, which serve as the voltage follower connection. Since the non-inversion input terminal serves as the gate of the P-channel MOS transistor MP11, the switch S17 is closed. Then, it is connected to the input terminal Vin.
In this way, in accordance with the switching of the switches S11 to S18, there are the two states. The two states are switched for every frame (or in one horizontal period). Actually, a polarity inversion signal that is switched for each horizontal period is used to switch the switches S11 to S18 in many cases. In the states of the switches shown in FIG. 1A, it is supposed that an offset voltage (+Vos) is tentatively generated. When the switches S11 to S18 are switched which leads to the states of the switches shown in FIG. 1B, the offset voltage becomes −Vos. Thus, when those switches S11 to S18 are switched for every frame (or in one horizontal period), the offset is spatially dispersed. Then, the offset voltages are averaged to zero. Therefore, the averaged voltage, namely, the offset voltage is recognized as zero by the human's eye. In other words, this is the method to deceive the human's eye.
FIG. 2 shows a circuit diagram of a typical amplifier disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-326529). This amplifier is not of a type for switching the switches and canceling the offset, differently from the amplifier shown in FIG. 1. With reference to FIG. 2, the amplifier can be considered by dividing into an input stage 21, a middle stage 22 and a final stage 23. The input stage 21 includes P-channel MOS transistors MP20, MP21 and MP22 and N-channel MOS transistors MN20, MN21 and MN22. The middle stage 22 includes P-channel MOS transistors MP23, MP24, MP25, MP26, MP27 and MP28, and the N-channel MOS transistors MN23, MN24, MN25, MN26, MN27 and MN28. The final stage 23 includes a P-channel MOS transistor MP29 and an N-channel MOS transistor MN29. The amplifier further includes phase compensation capacitors C21, C22 between the middle stage 22 and the final stage 23.
In the P-channel MOS transistors MP21 and MP22, their sources are commonly connected, and a P-channel differential pair is generated. The P-channel MOS transistor MP20 is connected between this P-channel differential pair and a positive power source VDD2. In the P-channel MOS transistor MP20, its source is connected to the positive power source VDD2, its drain is connected to the commonly connected sources of the P-channel MOS transistors MP21 and MP22, and its gate is connected to a constant voltage source terminal BP21. The P-channel MOS transistor MP20 acts as a constant current source.
In the N-channel MOS transistors MN21 and MN22, their sources are commonly connected, and an N-channel differential pair is generated. The N-channel MOS transistor MN20 is connected between this N-channel differential pair and a negative power source VSS2. In the N-channel MOS transistor MN20, its source is connected to the negative power source VSS2, its drain is connected to the commonly connected sources of the N-channel MOS transistors MN21 and MN22, and its gate is connected to a constant voltage source terminal BN21. The N-channel MOS transistor MN20 acts as a constant current source. The gate of the P-channel MOS transistor MP21 and the gate of the N-channel MOS transistor MN21 are connected to an input terminal INN. The gate of the P-channel MOS transistor MP22 and the gate of the N-channel MOS transistor MN22 are connected to an input terminal INP. The drain of the P-channel MOS transistor MP21 is connected to a connection node C between the drain of the N-channel MOS transistor MN23 and the source of the N-channel MOS transistor MN25 in the middle stage 22. The drain of the P-channel MOS transistor MP22 is connected to a connection node D between the drain of the N-channel MOS transistor MN24 and the source of the N-channel MOS transistor MN26. The drain of the N-channel MOS transistor MN21 is connected to a connection node A between the drain of the P-channel MOS transistor MP23 and the source of the P-channel MOS transistor MP25. The drain of the N-channel MOS transistor MN22 is connected to a connection node B between the drain of the P-channel MOS transistor MP24 and the source of the P-channel MOS transistor MP26.
In the P-channel MOS transistors MP23 and MP24, their sources are connected to each other, and their gates are connected to each other. The commonly connected sources are connected to the positive power source VDD2. The drain of the P-channel MOS transistor MP23 is connected to the node A. The drain of the P-channel MOS transistor MP24 is connected to the node B. In the P-channel MOS transistor MP25, its source is connected to the node A, its drain is connected to the commonly connected gates of the P-channel MOS transistors MP23 and MP24, the source of the P-channel MOS transistor MP27 and the drain of the N-channel MOS transistor MN27. In the P-channel MOS transistor MP26, its source is connected to the node B, and its drain is connected to the source of the P-channel MOS transistor MP28, the drain of the N-channel MOS transistor MN28 and the gate of the P-channel MOS transistor MP29. The gates of the P-channel MOS transistors MP25 and MP26 are commonly connected and further connected to a constant voltage source terminal BP22. In the N-channel MOS transistors MN23 and MN24, their sources are connected to each other, and their gates are connected to each other. The commonly connected sources are connected to the negative power source VSS2. The drain of the N-channel MOS transistor MN23 is connected to the node C. The drain of the N-channel MOS transistor MN24 is connected to the node D. In the N-channel MOS transistor MN25, its source is connected to the node C, its drain is connected to the commonly connected gates of the N-channel MOS transistors MN23 and MN24, the source of the N-channel MOS transistor MN27 and the drain of the P-channel MOS transistor MP27. In the N-channel MOS transistor MN26, its source is connected to the node D, and its drain is connected to the source of the N-channel MOS transistor MN28, the drain of the P-channel MOS transistor MP28 and the gate of the N-channel MOS transistor MN29. The gates of the N-channel MOS transistors MN25 and MN26 are commonly connected and further connected to a constant voltage source terminal BN22.
In the P-channel MOS transistor MP27, its gate is connected to a constant voltage source terminal BP23, its source is connected to the drain of the P-channel MOS transistor MP25, and its drain is connected to the drain of the N-channel MOS transistor MN25. In the N-channel MOS transistor MN27, its gate is connected to a constant voltage source terminal BN23, its source is connected to the drain of the N-channel MOS transistor MN25, and its drain is connected to the drain of the P-channel MOS transistor MP25. The P-channel MOS transistor MP27 and the N-channel MOS transistor MN27 act as a floating constant current source. In the P-channel MOS transistor MP28, its gate is connected to a constant voltage source terminal BP24, its source is connected to the drain of the P-channel MOS transistor MP26, and its drain is connected to the drain of the N-channel MOS transistor MN26. In the N-channel MOS transistor MN28, its gate is connected to a constant voltage source terminal BN24, its source is connected to the drain of the N-channel MOS transistor MN26, and its drain is connected to the drain of the P-channel MOS transistor MP26. The P-channel MOS transistor MP28 and the N-channel MOS transistor MN28 act as the floating constant current source. The P-channel MOS transistor MP29 is the output transistor where its source is connected to the positive power source VDD2, its gate is connected to the source of the P-channel MOS transistor MP28, and its drain is connected to the output terminal OUT. The N-channel MOS transistor MN29 is the output transistor where its source is connected to the negative power source VSS2, its gate is connected to the source of the N-channel MOS transistor MN28, and its drain is connected to the output terminal OUT.
In the phase compensation capacitor C21, one end is connected to the node B, and the other end is connected to the output terminal OUT. In the phase compensation capacitor C22, one end is connected to the node D, and the other end is connected to the output terminal OUT.
A differential amplifier shown in FIG. 2 is a so-called Rail-to-Rail amplifier. The input stage 21 has the differential stage configuration in which the differential pair of the P-channel MOS transistors and the differential pair of the N-channel MOS transistors are combined, in order to attain the Rail-to-Rail. Thus, the output of the differential pair of the P-channel MOS transistors and the output of the differential pair of the N-channel MOS transistors are required to be added. For this reason, a differential stage output is connected to each of the node A, the node B, the node C and the node D in a so-called folded cascode connection. With such a connection, the outputs of the differential pair of the P-channel MOS transistors and the differential pair of the N-channel MOS transistors are current-added. With such a configuration, the differential pair of the N-channel MOS transistors is operated in the range of the input signal where the differential pair of the P-channel MOS transistors is not operated. On the contrary, the differential pair of the P-channel MOS transistors is operated in the range of the input signal where the differential pair of the N-channel MOS transistors is not operated. As a result, it is possible to obtain the input stage for the operation in the input ranges of all of the power source voltages.
As mentioned above, the P-channel differential amplifier for canceling the offset can be treated by the circuit shown in FIG. 1, and the design based thereon does not bring about any problem. Also, in case of the N-channel differential amplifier, this can be attained only by inverting the polarity of the transistor in FIG. 1. However, in the differential amplifier other than them, there is a case that the idea similar to FIG. 1 cannot be applied. For example, if the principle similar to FIG. 1 is applied to the differential amplifier shown in FIG. 2, the circuit becomes very complex. The desirable operation cannot be attained even if the transistors acting as the active loads are switched simply as indicated in FIG. 1. That is, the desirable operation cannot be attained even if the inputs and outputs of the current mirror circuit composed of the P-channel MOS transistors MP23 to MP26 and the N-channel MOS transistors MN23 to MN26 are switched to then change the connections to the gates of the output transistors MP29, MN29. It is necessary to switch all of the connections to the active loads and the transistors MP27 and MN27 for determining an idling current of the middle stage 22 and the connections between the output transistors MP29 and MN29 and the transistors MP28 and MN28 for determining an idling current of the final stage 23. Trying to attain them results in a problem that the number of the switches required to switch is enormous.